Abstract:

New challenges and opportunities in process and design continue to emerge in parallel to ever shrinking semiconductor device geometries. While Moore’s law and beyond are driving scale reduction, the industry is facing increased process sensitivity and complexity, and is redefining on-wafer defect tolerance in terms of size and complexity.

While Moore’s law and beyond are driving scale reduction, the industry is facing increased process sensitivity and complexity, and is redefining on-wafer defect tolerance in terms of size and complexity. To detect, identify, understand the source and eliminate yield limiter defectivity are key for total wafer environment contamination characterization and control and are essential for yield enhancement to ensure the success of the latest technology nodes.

It is more imperative than ever that the semiconductor industry works together to enable improved defect detection, speciation/characterization metrology, and as needed, hybrid analytical technology for upcoming HVM readiness.

This presentation will look into the capabilities and limitation of currently deployed particle sizing technologies for liquid and introduce new technologies that may help bridge the gap between current and next-generation nodes.